The present invention relates generally to synchronous rectifier circuits, and more particularly to xe2x80x9cbuckxe2x80x9d, xe2x80x9cboostxe2x80x9d and other switching voltage converter circuits (i.e., voltage regulator circuits) that include synchronous rectifier circuits, and still more particularly to such voltage converter circuits which operate with reduced power dissipation and improved efficiency.
FIG. 1 shows a conventional buck switching voltage converter 1 that includes a synchronous rectifier. The synchronous rectifier includes a large, low-resistance MOS N-channel transistor M2 having its source connected to a ground conductor 3, its gate being coupled by logic circuitry 14 to the output of a comparator 12 having its (+) input connected to a ground conductor 3 and its (xe2x88x92) input connected by conductor 5 to the drain of transistor M2. Logic circuitry 14 typically includes a latch circuit that prevents comparator 12 from turning transistor M2 on more than once during each switching cycle. This can occur if the offset of comparator 12 is negative and causes transistor M2 to be turned off xe2x80x9cearlyxe2x80x9d, in which case the magnitude of the VDS voltage between the drain and source of transistor M2 rapidly increases to equal the forward bias voltage of a xe2x80x9cbody diodexe2x80x9d D and then decreases back down to the threshold voltage of comparator 12. Transistor M2 inherently includes the drain-to-substrate body diode D, with its N-type cathode region common with the drain and its P-type anode connected to the source of transistor M2.
Voltage converter circuit 1 also includes an input conductor 2 receiving an unregulated voltage Vin and applying it to the drain of an N-channel switching transistor M1. The source of transistor M1 is connected by conductor 5 to the drain of transistor M2 and to a first terminal of an inductor 6 having an inductance L. A second terminal of inductor 6 is connected by an output conductor 7 to a first terminal of a load or output capacitor 8 having a capacitance C. As is well known to those skilled in the art, an inductor current IINDUCTOR flows back and forth between inductor 6 and capacitor 8 during operation of voltage converter circuit 1. The second terminal of load capacitor 8 is connected to ground conductor 3. A regulated output voltage Vout is produced on output conductor 7. The regulated output voltage Vout is applied to an input of a feedback control circuit 19 that compares Vout with a reference voltage and accordingly produces a signal on conductor 4 to control the switching of transistor M1 so as to cause voltage regulator circuit 1 to maintain the desired regulated value of Vout.
In any integrated circuit manufacturing process, the comparator (such as comparator 12FIG. 1) has an inherent offset voltage, which may be positive or negative. The value of the comparator offset voltage produced by any particular integrated circuit manufacturing process has a statistical distribution.
In operation, switching transistor M1 is turned on during the initial part of each switching cycle. This causes current to flow from the source of the unregulated voltage Vin through transistor M1 and inductor 6 such that conductor 7 supplies current to maintain the desired value of output voltage Vout across a load capacitor 8 that may be connected to conductor 7 and/or across any additional external load that may be connected to conductor 7. During this portion of the switching cycle, the voltage of conductor 5 is high, so the output of comparator 12 is at a logical xe2x80x9c0xe2x80x9d level. The low xe2x80x9c0xe2x80x9d output voltage produced by comparator 12 causes logic circuit 14 to keep transistor M2 turned off. The flow of IINDUCTOR into load capacitor 8 increases the value of Vout to the desired regulated value determined by a reference voltage within feedback control circuit 19, which then produces a signal on conductor 4 that abruptly turns switching transistor M1 off.
The current IINDUCTOR cannot change abruptly, and therefore continues to flow from conductor 5 through inductor 6 and conductor 7. This causes the voltage on conductor 5 to rapidly decrease to a level approximately 600 millivolts below ground, at which point body diode D becomes forward biased enough to supply the current IINDUCTOR. The low voltage on conductor 5 causes comparator 12 to switch, causing it to produce a high logical xe2x80x9c1xe2x80x9d output level. That causes logic circuit 14 to produce a high voltage level on the gate of transistor M2 after a short delay, turning transistor M2 on.
The size of transistor M2 is selected so that when it is turned on, its channel resistance (Ron) is low enough that its drain-to-source voltage VDS is reduced from the approximately 600 millivolt forward bias voltage of body diode D to only approximately 100 millivolts (which reverse biases body diode D). Therefore, the power dissipation due to the flow of IINDUCTOR through transistor M2 after it is turned on is much lower than the power dissipation due to the flow of IINDUCTOR through body diode D before transistor M2 is turned on. After transistor M1 is turned off, the magnitude of IINDUCTOR gradually decreases at the rated (IINDUCTOR)/dt=Vout/L. Therefore, the drain-source voltage VDS voltage of transistor M2 decreases at roughly the same rate as IINDUCTOR until the VDS of transistor M2 is equal to the offset voltage of comparator 12, which typically can be as large as approximately 10 millivolts above or below ground.
Typically, the size of transistor M2 is chosen so that when the maximum value of IINDUCTOR is flowing through the channel resistance of transistor M2, its VDS voltage is approximately equal to the above mentioned 100 millivolts. The 10 millivolt offset voltage of comparator 12 typically corresponds to roughly 10 percent of the maximum value of IINDUCTOR. If, for example, the magnitude of the offset voltage of comparator 12 is 10 millivolts, the decreasing VDS voltage causes comparator 12 to turn off transistor M2 either too soon or too late, depending on whether the offset voltage is positive or negative. In either case, the power dissipation is substantially increased. If the offset voltage is negative, transistor M2 is turned off too late, and then it draws current from load capacitor 8 and any additional load that is connected to output conductor 7. Even if the net current flow out of conductor 7 to an external load (not shown) is zero, IINDUCTOR at that time has a value equal to approximately 10 percent of the maximum current through inductor 6 and oscillates between inductor 6 and load capacitor 8, and also flows through the channel resistance of transistor M2 and dissipates power therein.
If the comparator offset voltage is positive, then transistor M2 will be turned off too soon. In that case, there is still up to approximately 10 percent of the maximum inductor current still flowing in inductor 6, and it flows through the large 600 millivolt forward bias voltage of body diode D, and consequently dissipates a large amount of power.
Thus, the prior art buck voltage converter 1 of FIG. 1 is characterized by decreased conversion efficiency for either positive or negative offset voltages of comparator 12.
Synchronous rectifier circuits of the kind described above also can be used in motor control circuits, class D audio amplifiers, and other circuitry.
Thus, there is an unmet need for an improved synchronous rectifier that accomplishes improved conversion efficiency when used in a utilization circuit such as an integrated circuit voltage converter, a motor control circuit, a class D audio amplifier, or the like.
Accordingly, it is an object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a utilization circuit.
It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a signal conversion circuit.
It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a voltage converter circuit.
It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a buck voltage converter circuit.
It is another object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a boost voltage converter circuit.
It is another object of the present invention to provide an improved synchronous rectifier circuit which avoids the above described problems of the prior art.
It is another object of the invention to provide an improved voltage converter circuit including a synchronous rectifier.
It is another object of the invention to avoid undesirable effects of delay through a comparator in a synchronous rectifier of a voltage converter or other utilization device such as a motor control circuit or a class D audio amplifier to decrease power dissipation.
Briefly described, and in accordance with one embodiment, the present invention provides a synchronous rectifier circuit suitable for use in conjunction with a utilization circuit such as a signal conversion circuit. In its broadest aspects, the synchronous rectifier circuit includes a comparator (120) having first input coupled to a first conductor (5) and a second input coupled to a reference voltage conductor (3). Typically, the first conductor conducts a current that also flows through an inductor. The synchronous rectifier circuit includes a logic circuit (140) having an input coupled to an output (13) of the comparator, a first output (15), and a second output (9), a first transistor (M2-1) having a gate coupled to the first output (15), a source coupled to the reference voltage conductor (3), and a drain coupled to the first conductor (5), and a second transistor (M2-2) having a gate coupled to the second output (9), a source coupled to the reference voltage conductor (3), and a drain coupled to the first conductor (5).
In the described embodiments, the synchronous rectifier circuit is included in a voltage converter circuit. In one embodiment the synchronous rectifier circuit includes a comparator (12) having an inverting input coupled to a first conductor (5) and a non-inverting input coupled to a reference voltage conductor (3), a logic circuit (140) having an input coupled to an output (13) of the comparator, a first output (15), and a second output (9), and transistor circuitry including first and second transistor sections. The first transistor section (M2-1) has a gate coupled to the first output (15), a source coupled to the reference voltage conductor (3), and a drain coupled to the first conductor (5). The second transistor section (M2-2) has a gate coupled to the second output (9), a source coupled to the reference voltage conductor (3), and a drain coupled to the first conductor (5). The logic circuit (140) is operative to turn on both the second transistor section (M2-1) and the third transistor section (M2-2) in response to a first switching of the comparator (12) to a xe2x80x9c1xe2x80x9d level, and to turn off only the first transistor section (M2-1) in response to a second switching of the comparator to the xe2x80x9c1xe2x80x9d level, and to turn the off second transistor section (M2-2) in response to a third switching of the comparator to the xe2x80x9c1xe2x80x9d level. The logic circuit (140) also is operative to turn on both the second transistor section (M2-1) and the second transistor section (M2-2) in response to a first switching of the comparator from a xe2x80x9c0xe2x80x9d level to a xe2x80x9c1xe2x80x9d level and to turn off the first transistor section (M2-1) if the comparator does not then switch from the xe2x80x9c1xe2x80x9d level to the xe2x80x9c0xe2x80x9d level within a predetermined delay.
The voltage converter circuit includes a first transistor (M1) having a drain connected to receive an unregulated input voltage (Vin), a gate connected to receive a feedback control signal (4), and a source connected to a first conductor (5). An inductor (6) includes a first terminal coupled to the first conductor (5) and a second terminal connected to produce a regulated output voltage (Vout) on an output conductor (7). A load or output capacitor (8) is coupled between the output conductor and a reference voltage conductor (3). A feedback control circuit (19) is coupled between the gate of the first transistor (M1) and the output conductor for regulating switching of the first transistor in response to the regulated output voltage (Vout) so as to maintain it at a desired value.
In another embodiment the synchronous rectifier is included in a boost voltage regulator.